A Single Event Upset (SEU) is a condition in which a circuit element changes state as a result of a charged particle impacting at or near a transistor junction. The collision of the charged particle with the junction can induce an upset to the state of the transistor. In the case of a memory cell, the change in state is a bit flip where the value of a bit stored in the memory cell changes from a 0 to a 1 or from a 1 to a 0. Vulnerability to SEUs may be expressed in terms of a Failure in Time (FIT) rate. FIT rate is typically expressed as the number of failures that are expected for one billion IC-hours of operation.
Within the semiconductor industry, FIT rate is typically expressed on the IC level. In the case of some programmable ICs, for example, field programmable gate arrays (FPGAs), FIT rate is dependent upon the actual circuit design that is loaded into the IC. In the usual case, determining a circuit design-specific FIT rate is a time consuming and complex endeavor. Specialized Intellectual Property (IP) cores that detect occurrences of SEUs are incorporated into a circuit design, which is then loaded into the IC. A large number of fault injections are performed to obtain statistically meaningful data. A fault injection is an artificial technique for inducing an SEU event in an FPGA static random access memory (SRAM) cell. Detecting design failures often requires providing a set of input vectors to the IC with the circuit design loaded therein, and observing results.